The invention relates to semiconductor device fabrication techniques and, more particularly, to techniques for etching through a dielectric layer to an underlying silicide layer.
Typically, source and drain regions in a modern MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) devices are formed with overlying silicide as the contact. Silicides are alloys of silicon and metals, and are used as contact materials in silicon device manufacturing. Exemplary silicides are cobalt silicide (CoSi2), nickel Silicide (NiSi), titanium silicide (TiSi2), tungsten silicide (WSi2), tantalum silicide (TaSi2), and platinum silicide (PtSi).
Silicides are commonly used as conductors and contact materials in silicon semiconductor technology due to their high conductivity, compatibility with silicon, and suitability to small-geometry semiconductor devices. The high conductivity (low resistivity) of source/drain silicide serves to minimize the contribution of parasitic resistance in the source drain region to the series resistance of MOSFET devices that employ it. The parasitic series resistance of silicide itself is often so small that its contribution to total series resistance is considered to be negligible and not a limiting factor to device performance.
In the MC (Metal Contact) RIE (Reactive Ion Etching) process, due to poor selectivity of nitride RIE and silicide, MC RIE is normally etched into silicide. In 90 nm technology for silicon on insulator (SOI), because of thin Si, sometimes the MC RIE punches through the silicide and touches the surface of Si which causes weak driving current problems or contact resistance problems.
It is well known that SiO2 can be used to act as a good RIE stop for the nitride RIE. Normally, silicide is covered with nitride which has a poor selectivity between nitride RIE and silicide. In order to protect the silicide from nitride etch, a thin oxide layer between silicide and nitride as an etch stop is preferred. However, conventional SiOx deposition can cause the oxidation of silicide and it creates a resistance problem. In order to avoid the oxidation of silicide, a thin oxide layer on top of silicide is preferably applied at room temperature.
Reactive Ion Etching (RIE) is a variation of plasma etching in which, during etching, a semiconductor wafer is placed on a RF (radio frequency) powered electrode. The wafer takes on a potential which accelerates etching species extracted from the plasma toward the etched surface. The chemical etching reaction is preferentially taking place in the direction normal to the surface, i.e. etching is more anisotropic than in plasma etching but is less selective. Although RIE leaves the etched surface damaged, it is a very common etching mode in semiconductor manufacturing.
FIGS. 1A and 1B illustrate a process 100 of the prior art, for etching through a dielectric layer to an underlying silicide layer of a semiconductor device.
A layer 104 of single crystalline silicon is bonded on a semiconductor (single crystal silicon) substrate (wafer) 101 through buried oxide 102 (BOX). The layer 104 typically has a thickness of 500-700 Angstroms. This is a typical vendor-supplied SOI (Silicon On Insulator) wafer. The silicon substrate 101 is shown much thinner than in reality (i.e., not to scale), for illustrative clarity.
A layer 106 of silicide is formed atop the layer 104 of single crystalline silicon. The silicide layer 106 typically has a thickness of about 200-300 Angstroms, and is suitably formed by traditional salicidation process (deposit metal, heat, etch, heat again). An area 107 disposed on the side of layer 104 and 106 is shallow trench isolation (STI).
A layer 108 of nitride is used to cap the silicide layer 106. The nitride layer 108 typically has a thickness of about 500 Angstroms, and is suitably formed by Chemical Vapor Deposition (CVD). Silicon Nitride (Si3N4; often referred to simply as “nitride”; often abbreviated as “SiN”) is a dielectric material which is commonly used to provide an excellent mask (barrier) against oxidation of silicide during the subsequent dielectric deposition 110 such as SiOx deposition at high temperature.
A layer 110 of dielectric material is formed over the nitride layer 108. The dielectric layer 110 typically has a thickness of about 5000 Angstroms, and is suitably formed by CVD.
Then, MC (Metal Contact) RIE is performed to open a via (contact hole) 112, through the layers 110 and 108, to the underlying silicide 106. (MC RIE in general refers to both the dielectric and nitride etch (one process). (The RIE chemistry changes during the contact etch.) The resulting structure is shown in FIG. 1B.
Finally, a thin layer (liner) of Ti/TiN (titanium nitride), not shown, is deposited in the contact hole 112, which is ultimately filled with a conductor such as tungsten (W).
As best viewed in FIG. 1B, during MC RIE, the underlying silicide layer 106 is compromised (thinned, etched). This becomes a problem when the silicide 106 is thin and the Ti/TiN liner would then land on top of the silicon 104 instead of on the silicide 106, and this can cause a contact resistance problem. In the extreme case, MC RIE with sputter clean can cause the bottom of the MC to penetrate into the silicon and touch the bottom of Si (or top of buried oxide surface).
A solution to this problem is simply to ensure that the silicide layer 106 is thick enough to withstand some etching during MC RIE. However, the downside of such an approach would be Si consummption and contact resistance problems. In bulk (non SOI) technology, the problem would be junction leakage.